1. Field of the Invention
The present invention relates in general to a semiconductor memory device, and more particularly, to a deep trench capacitor structure of a volatile memory cell with an improved isolation structure, and method for forming the same.
2. Description of the Related Art
A typical dynamic random access memory cell (DRAM) is composed of a switching transistor and a coupled storage capacitor. 512 MB DRAM is now widely available. There has been still an increased interest in the electronic industry for higher density and higher speed memory cell devices. Research and development efforts are made on an ongoing basis to develop faster and, correspondingly, smaller DRAM devices. Currently, conventional 2D design is gradually being replaced by 3D vertical design in DRAM fabrication. Areas transistors and capacitors occupy on a DRAM cell is greatly reduced by fabricating the capacitor in a deep trench in a semiconductor substrate, thereby minimizing the size of memory cells and power consumption and also increasing operating speeds.
FIG. 1 shows a conventional deep trench structure of a DRAM cell. As shown in FIG. 1, a deep trench (DT) 11 is formed in a p-type semiconductor silicon substrate 10. A deep trench capacitor 12 is then fabricated on the bottom portion of DT 11, which includes a buried plate 14; a node dielectric layer 16 and a storage node 18. The deep trench (DT) 11 can be conventionally formed in the p-type semiconductor substrate 10 by reactive ion etching (RIE). A high-temperature and short-term annealing process using a heavily-doped oxide material (such as arsenic silica glass (ASG)) is then performed. N+ ions are diffused into the silicon substrate 10 at the lower portion of the deep trench DT 11, thus forming an n+-type diffusion region 14 to serve as the buried plate of the deep trench capacitor 12. A silicon nitride liner 16 is then formed on the bottom and lower portion sidewall of the trench 11, serving as a node dielectric layer. N-doped polysilicon is deposited into the deep trench 11 and recessed to a predetermined thickness, which serves as storage node 18 of the deep trench capacitor 12.
After a deep trench capacitor 12 is formed in p-type semiconductor substrate 10, a collar insulating layer 20 is formed, lining the sidewall of the deep trench 11 above the deep trench capacitor 12, and recessed to a predetermined depth. Second and third n-doped polysilicon layers 22 and 24 are then deposited onto the deep trench capacitor 12 sequentially. One side of the third polysilicon layer and a portion of the second polysilicon are etched to form shallow trench isolation (STI) structure 26 to isolate two adjacent memory cells. Word lines WL1 and WL2, source/drain regions 28, a bit line contact plug (CB) and a bit line (BL) are fabricated subsequently on/in the p-type silicon substrate 10. With a thermal process, the n-type dopants in the third polysilicon layer 24 diffuse into the contiguous silicon substrate 10 from the side without collar insulating layer 20 to form a buried strap 30 that fuses to source/drain region 28 as a node junction and connects the third and second polysilicon layers 22 and 24 and the deep trench capacitor 12 in the deep trench 11.
However, seams or crystal lattice defects occur when shrinking shallow trench isolation structures, thereby reducing the reliability of memory cells.